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Branch:
Electrical and Electronics Engineering
Placement Session:
2022-2023
Offer obtained:
FTE+6 month intern(optional)
Description of role:
NA
Job location:
Bangalore
Eligible Branches:
Analog/Digital Engineering :
B.Tech ECE EEE M.Tech ECE EEE
Chem (Systems and Control)
Embedded Software FTE:
B.Tech CSE ECE EEE M.Tech CSE ECE EEE
Eligibility Criteria:
CGPA Cutoff 6 (Students with borderline CGPAs cannot apply)
NO ACTIVE BACKLOGS
Selection Procedure:
Round 1 -OT
Round 2 -1 or 2 Technical rounds
Description of Online test:
It was conducted on the Hirepro platform
we can choose profiles for OT during registration
Analog, Digital, and Embedded systems (we can choose all Three)]
I chose Analog/Digital.
Digital 20 questions 40 minutes
Analog 20 questions 40 minutes
Aptitude 20 questions 30 minutes
Digital
Most of the questions related to
Counters, duty cycle,
Flipflops, shift registers, static timing analysis, Verilog snippets
Analog
It contained questions on Circuit Theory, buffers, inverters, Mosfets, BJTs, and Opamps circuits.
Most questions are related to switching circuits with diodes, capacitors, and resistors.
Aptitude
aptitude section was easy, Accuracy and Time management are key
overall difficulty moderate
Each section has its cutoffs.
Description of Technical Interview:
Analog
48 members were selected for Analog interviews (9 panels)
They started with a quick introduction.
The interviewer was cool; He did not ask anything from my resume.
He started with an RC circuit with an input square wave voltage source (the time constant of the RC circuit is the same as the ON time of the wave)
-voltage waveform at different points in the circuit
Then he asked me to draw the same waveforms with the input square wave current source.
Then he moved nmos circuit questions like
What is the gain, output impedance, input impedance, etc.
Then he replaced nmos with pmos, and finite gain op map is connected to pmos gate terminal 3-4 questions related to that.
I remembered a question.
How do you make connections such that it becomes a negative feedback circuit?
He slowly increased the complexity of the same circuit and added capacitors across Rload and at the output of Opamp.
Questions like
No of poles and zeros in the circuit and What are they (without using pen and paper)
Impact of pole and zero on the system
Which one is the dominant pole
draw bode plot.
It lasted for 1 hour.
Six final selects
Digital
Eight members were selected for Digital Interviews (1 panel)
He also started with my Quick introduction
He started with questions related to universal gates.
Minimum no of nor and nand required for the given Boolean function
Number of half and full adder circuits required to know the numbers of 1's in the given 5-bit binary number
Given input waveforms of the sequential circuit and asked me to draw output waveform.
Some questions related to the Finite State Machine
3-4 questions related to Static Timings Analysis for a given circuit.
3-4 questions related to cross-domain clocking and asynchronous FIFO.
It lasted for 1hr 10min
Three final selects
Description of HR Round:
It was a 10 min phone call.
It started with my brief introduction.
She asked If I was given a chance to choose analog or digital, which one I chose, and why. (I said Digital) (Fortunately, I was selected for both analog and digital, so she asked me to choose one)
And some standard questions like
Are you willing to go for higher studies, and why? obvious Ans NO
Do you have any questions? Be ready with at least one question.
Preparation Strategy:
If you have decided and have clarity about the path(core/code/hardware etc.) you want to go, then you are half done.
3-4 months of serious preparation is needed for Hardware; more than this is well and good.
Be thorough with Verilog or VHDL.
Prepare short notes and revise them multiple times.
Practice the previous year's analog and digital GATE questions
Pay attention to aptitude, and practice a lot to improve speed and accuracy, which matters lot in OT.
Some hardware companies ask software questions in OTs and interviews; basic software knowledge is always advantageous.
Have At least one good project on your resume.
Have a preparation group of 2-3 members to clear concepts and make group projects
Try to cover the topics mentioned in their preparation guide for Texas instruments.
Be strong with your basics
Resources:
Digital Electronics: Morris mano or Anand Kumar textbook, Unacedemy YouTube videos
Analog Electronics: Behzad Razavi Electronics-1 and Unacedemy YouTube videos
Verilog: NPTEL lectures, Samir Palnitkar textbook, HDL bits website for practice
Digital Integrated circuits: Jan Rabaey(YouTube)
Static timing analysis: vlsiexcept website
Cross-domain clocking: Sunburnt design paper
Microprocessor and computer organization: Lecture notes and any YouTube videos
Aptitude: indiabix
C++concepts: gfg(some hardware companies need basic software knowledge)
examside website for EEE and ECE previous year's GATE papers
Additional info for our viewers:
It is always good to start early, but there is always time to start. I started in mid-February.
However, start as early as possible.
Take help from seniors and friends, many good people are there to guide you throughout your preparation, but it is your responsibility to take the initiative to get guidance.
It is okay if you miss interns. You will get a chance to bounce back—many of my friends who did not get interns placed in high CTC companies. Just focus on your work.
Know your mistakes, try to overcome them, do your work, and leave the rest to God.
Be calm and confident while giving interviews.
All the best