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Branch:
Electrical and Electronics Engineering
Session:
2023-2024
Offer obtained:
6 months internship + FTE
Description of role:
We design, develop, and test forthcoming chips for hand-held devices in the market. We collaborate with cross-functional teams to ensure performance, reliability and power efficiency of the chip, while also staying updated with emerging technologies and industry standards.
Job/Intern location:
Noida
Eligible Branches:
ECE, EEE
Eligibility Criteria:
Selection Procedure:
Round 1 : Online test
Round 2: Technical Interview 1
Round 3 (if passed round 2) : Technical Interview 2
Description of Online test:
Online test had three sections with a total of 60 questions.
The first section comprised of aptitude (mainly probability and statistics). Some questions were based on Bayes theorem and other known probability theorems. Some were paragraph type with tabular data (data interpretation and analysis type scenario). Some questions were based on the scenario of blue, black, red balls probability sums. Many questions were continuation of previous scenarios. Other than that grammar was there.
The second section comprised of digital and analog design. There were questions from MOSFET, CMOS and BJT biasing. Digital questions were from counters, MUXes, least timing requirements for which data-path and how much time is required and from Karnaugh map.
The last section was of coding. It comprised of output type questions. For all the questions mostly a huge code was given and some outputs were listed and one had to be chosen. Some were asked from trees, linked list etc. Like which data structure has least time complexity, in a given scenario which data structure to use etc.
Description of Technical Interview:
There were two rounds for me.
The first round was of 1 hour 10 mins. They started asking me from soc design, metastability, clbs , fpga design and its timings. Then they moved on to static timing analysis and asked me about toggle flop synchronisers, and other types. There were about like 5-6 questions on verilog coding, then making of different logics using muxes as well as FSM design with verilog coding of it. They asked me about my project that I had done during my internship. In analog design, i was asked about bistable, astable mutlivibrators and the use cases.
The second round was of 1 hr 15 mins.
That round was also similar to the first one. Questions were asked both from analog and digital design. In the end, the interviewer asked me puzzles.
Description of HR Round:
NA
Preparation Strategy:
Study at least 4 books for analog design.
Study Morris Mano, Donald P Leach, NPTEL hardware modelling with verilog course etc for digital design, solve probability and statistics and aptitude questions.
Resources:
As mentioned in the previous part
Additional info for our viewers:
Maintain a very good CGPA. Trust me, it helps.