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Branch:
Electronics and Communication Engineering
Session:
2021-2022
Offer obtained:
Internship
Description of role:
NA
Job/Intern location:
Hyderabad
Eligible Branches:
CSE, ECE, EEE
Eligibility Criteria:
NA
Selection Procedure:
Round 1 - OT
Round 2 - Technical Interview
Round 3 - HR Interview
Description of Online test:
Hardware - Basics of digital system design and Verilog
Software - simple C++ and python based questions, questions on Operating system
Aptitude - generic
Description of Technical Interview:
Basic C++ program, explaining my project mentioned in the resume, some verilog based questions
Description of HR Round:
It was sort of a mix of HR and technical. It began with talking about the 2 projects I mentioned in my resume, what was its aim, how it can be applied in the real world and what were the difficulties faced while developing it. Then it moved on to what I know about the company where I started explaining everything I knew about memory storage devices which is what the company manufactures. I tried to create an impression of being passionate about learning new things.
Preparation Strategy:
Perfect your basics and practice for OT. Give all the mock OTs that might be organized by any of your college associations. Don't be depressed if you don't perform well there, they are meant to point out what topics/subjects you need to work on. Video lectures are good but try to go through some good textbooks as well because you might find there some details that a lecture series might miss.
Resources:
NPTEL lecture series for detailed understanding of a topic if you want.
Neso and GeeksForGeeks for just the basics of all topics.
Additional info for our viewers:
For non CSE students, decide on which side you want to go early on, trying to prepare for both software and core profiles will hinder your preparations.